Method and apparatus for processing digital signals prior to recording

ABSTRACT

A method of processing digital information prior to recording comprises converting input digital words into code words, each of the same period as the input digital word but containing a greater number of time slots than the number of bit locations in the digital word, providing a plurality of groups of code words and selecting the group from which a code word will be taken in any instance on the basis of the immediately preceding code word. The code words are defined such that there is a minimum spacing of three time slots between transitions and no transition is permitted in the last time slot. Two main groups of code words are provided which each have a transformed version. Apparatus for carrying out the method as described as is apparatus for decoding the encode words in replay.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a method and apparatus for processingdigital signals prior to recording. More particularly but notexclusively the digital signals represent television video signals.

A channel code which had a minimum separation of 11/2 bit cells andwhich also was capable of statistically controlling the low frequencycomponents was described in our co-pending U.K. Application No.A-2,141,906. For each successive group of eight bits it is possible,theoretically, (at least on average) to identify just over 453 discretecombinations and this should make it possible to construct a blockcodewith controlled low frequencies with a minimum transition separation of11/2 bit cells.

An alternative proposal has been made which operates on a bit-by-bitbasis. Consideration has been given to the realisation of thisalternative proposal but there are a number of difficulties which stemfrom the combination of the necessary high speed, the look ahead and themodulo-three requirements of parts of the coder.

SUMMARY OF THE INVENTION

The present invention provides a method for processing digitalinformation for recording comprising the steps of inputting a successionof input digital words each comprising a plurality of bit locations,generating a respective code word for each digital word with each codeword being of the same duration as a digital word but having a number oftime slots greater than the number of bit locations in an input wordproviding a plurality of groups of code words, and selecting for eachdigital word a code word from one of the plurality of groups on thebasis of the immediately preceding code word used.

Preferably, in each code word there is a period of three time slotsbetween adjacent transitions. It is also advantageous to use more thantwo groups of code words e.g. two main groups may be used with each maingroup having a transformed or "opposite" group.

An advantage of the method is that less read only memory is requiredwhilst approaching close to the theoretical limit of just over 453different combinations in each block of 8 cells.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the present invention be more readily understood anembodiment thereof described by way of example with reference to theaccompanying drawings, in which :

FIG. 1 shows the basis of a first code book for 4-bit words;

FIG. 2 shows the basis of a second code book for 4-bit words;

FIG. 3 shows the time of transitions for certain combinations in thefirst and second code books;

FIG. 4 shows the basis of a first code book for 8-bit words;

FIG. 5 shows the basis of a second code book for 8-bit words;

FIG. 6 shows in block diagram form an encoder which utilizes the firstand second code books for 8-bit words;

FIG. 7 shows truth tables to assist understanding of the encoder shownin FIG. 6;

FIG. 8 shows in more detail one way in which a part of the encoder ofFIG. 6 may be implemented and is accompanied by its truth table;

FIG. 9 shows in block diagram form a decoder for decoding the signalencoded by the encoder of FIG. 6; and

FIGS. 10A-10J are a print out of the complete first and second codebooks.

DETAILED DESCRIPTION

Before describing the invention in detail, it is considered helpful toexplain some basic principles of the coding system being used. It is tobe remembered that the techniques disclosed in our co-pendingapplication identified above are still being used and attention isdirected to that case for further details. Suffice to say that thepresent invention comprises a method of processing digital informationfor recording purposes. The processing is organised on a word-basedarrangement and generates a code word for each input digital word to berecorded, the code word occupies the same time as the input digital wordbut has at least double the number of time slots with respect to thenumber of bit locations in an input digital word. In a code word,transitions are not permitted at specified locations.

For a minimum transition separation of three half cells, the number ofdifferent combinations which can be portrayed as the number ofhalf-cells increases from 0 to 34 is shown in the following table:

                                      TABLE 1                                     __________________________________________________________________________    0..1                                                                              6..13                                                                              12..129                                                                             18..1278                                                                            24..12664                                                                            30..125491                                        1..2                                                                              7..19                                                                              13..189                                                                             19..1873                                                                            25..18560                                                                            31..183916                                        2..3                                                                              8..28                                                                              14..277                                                                             20..2745                                                                            26..27201                                                                            32..269542                                        3..4                                                                              9..41                                                                              15..406                                                                             21..4023                                                                            27..39865                                                                            33..395033                                        4..6                                                                              10..60                                                                             16..595                                                                             22..5896                                                                            28..58425                                                                            34..578949                                        5..9                                                                              11..88                                                                             17..872                                                                             23..8641                                                                            29..85626                                                                            etc.                                              __________________________________________________________________________

A way of preventing transitions from being less than three half-cellsspacing between blocks would be to arrange that there were twohalf-cells without transitions between the end of one block and thestart of the next. An eight bit data block, allowing for the twohalf-cells between blocks, would leave 14 half-cells for informationwhich can provide 277 combinations. This is significantly less than the453 combinations theoretically available on average, amounting to only61%. If a 16 bit data block could be realised, providing 30 informationslots and 125491 combinations, this would provide a number ofcombinations equivalent to 354 per eight bit data block. This is betterbut it is still far short of the 453 combinations theoreticallyavailable.

A much better coding strategy has been discovered and to illustrate theprinciple this will be described for a four bit-data block. This codingstrategy uses two alternative Code Books `A` and `B` and the basis foreach of these is shown in FIGS. 1 and 2 respectively.

In Code Book `A` there is a first range (A) in which transitions arebarred in time slots 0 and 1 in the word being coded and also in thesubsequent word. A `O` in a time slot indicates that a transition is notpermitted, a `:` indicates that a transition is permissible providing notwo transitions are closer than three half-cells. There are 13combinations of patterns and for this first range (A) the subsequentword will also be coded on the basis of Book `A`. The second range `B`has word transitions barred in time slots 0,1,6,7 and there must be atransition in time slots 0 or 1 of the following word i.e. within thebrackets. Note however that the choice of the two positions will bedetermined by the next 4-bit word. This second range (B) provides afurther 6 combinations making 19 in all available for Code Book `A`.When the range `B` is used for one word the next word must be coded onthe basis of Code Book `B` shown in FIG. 2.

Again there are two basic ranges `A` and `B` but in this case each issplit into two giving sub-ranges A0, A1, B0 and B1. For A0 and B0 thereis a defined transition at time slot 0 whereas for A1 and B1 it is attime slot 1. A0 and A1 give 9 and 6 combinations respectively and forthese 15 cases the following word is coded on the basis of Code Book`A`. B0 and B1 give 4 and 3 combinations and for these 7 cases thefollowing word is coded on the basis of Code Book `B`. The total numberof combinations is therefore 22 for Code Book `B`.

For random data, Code Book (A) would be used on about 68% of occasions,Code Book (B) for the remainder, so the average number of combinationsfor every 4 bit-cells would be just under 20 or approximately 400combinations in eight bit-cells - an efficiency of about 88% of thetheoretical limit.

FIG. 3 shows the time of transitions for the 19 and 22 possiblecombinations in Code Books `A` and `B` respectively.

Since the number of available combinations exceeds the sixteen necessaryto carry 4 bits of binary information it is possible to eliminatepatterns having less desirable characteristics, for example the onehaving no transitions, and/or to allocate two different patterns tocertain 4 bit combinations. This may be most usefully realised byreplacing Code Book `A` by two alternatives Code Book `A` `same` andCode Book `A` `opposite`. For at least 13 of the 16 binary combinationsthe patterns stored in the alternative code books would be the same butfor three combinations the patterns in the `same` and `opposite`sections could differ. For these combinations the patterns would bechosen on the basis that the direct component due to the pattern wouldbe in the `same` or the `opposite` direction to the polarity existingimmediately before some sensible reference time for example just priorto time slot `0`.

If a `1` be stored to indicate a transition and a `0` to indicate notransition then the parallel information from the Read Only Memory whenserialised could cause a change of state of a divide by two counter togenerate the signal to be recorded.

The same type of splitting of Code Book `B` into sections `same` and`opposite` would be used but in this case at least 10 patterns wouldappear unchanged in both sections whilst 6 patterns could differ.

If an odd number of transitions occurs in a word then the polarity atthe reference time for the next word is reversed.

A total of six address bits for the ROM would be required and theseconsist of 4 for the binary date, one to select between Code Books `A`and `B` and one to select between `same` and `opposite`.

It might appear at first sight that nine output bits are required, eightto indicate the presence or absence of a transition in each of the 8time slots and one to instruct the ROM which of the Code Books `A` and`B` to use for the next 4-bit word.

By means of three 2-input gates, two binary digits giving four statescan be very easily used to produce the four possible patterns that canoccur by three consecutive time slots; these possible patterns consistof no transition or a transition in the first, second or third timeslot. It is also possible to use 5 bits to control transitions in 8 timeslots. Transitions in time slots 0 and 1 can only occur when Code Book`B` is in use and must occur in one of these positions so a simple ROMoutput bit may be used to control which of these two time slots mustcontain the transition.

If there is spare output capacity in the ROM it would be worthconsidering that one bit should be used to indicate if a word results inan odd or an even number of transitions since this is requiredinformation for the control of the direct component. Spare outputcapacity could also be used to give a measure of the direct componentbeing produced by each word but the sign of this must also take note ofthe polarity of the signal at the reference time.

Since there are many alternatives for the ROM system, which can eveninclude direct generation of the signal to be recorded by the ROM (butprobably in parallel form) it seems pointless giving ROM details andthat transition patterns are all that is necessary to define the channelcode.

So far the information has been on a 4-bit coder, obviously other sizesare possible and the one of particular interest is a coder for 8-bits.For such a coder FIGS. 4 and 5 show the basis of Code Books `A` and `B`which yield 406 and 466 combinations respectively. The average of thesewhen weighted for frequency of occurrence is about 425 or about 94% ofthat theoretically achievable.

The reason that a higher efficiency is not achieved stems from theoccasions when transitions in the 14 time slot are barred even when thenext transition is in time 1 of the next word.

To save space in providing information for the look-up table and to makecomputation easier, the number of transitions in time slots 0-15inclusive, the Code Book to use for the next word, and the time slots inwhich transitions occur, are combined in one 11 digit word. First digit(in the tens position) gives the number of transitions in time slots0-15 inclusive. The second digit (units position) gives which Code Bookis to be used for the following word O corresponds to A, 1 to B.

After the decimal point the first digit gives the address of the firsttransition, this never exceeds 8. The next pair and subsequent pairs ofdigits give addresses of the subsequent transitions but note that pairs00 do not signify a transition. For example in Code Book `B` or `1`level 16 `same` the number is 50.003081114. ##STR1##

In this particular case although it is from the `same` the magnitude ofthe shift of direct component happens to be zero as can be calculated.If `B` level 16 `opposite` had been selected the number would have been50.004071114 with transitions in the 0,4,7,11 and 14th time slots andthe shift would have been -2 i.e. a shift of 2 in the opposite directionto the polarity existing just before the zero time slot.

The number of address bits for the ROM will total 10, 8 for the data,one for differentiating between Code Books `A` and `B8` and one `same`or `opposite`. As mentioned earlier 1 output bit will suffice for timeslots 0 and 1, taken as a pair, and 2 bits for each of the triads 2--4,5-7, 8-10, 11-13 and 14-16 making 11 bits in all; to refer to time slot16 is incorrect but it can be used to control the selection between CodeBooks `A` or `B` to be used for the next 8-bit word. A total of 11output bits is required and since 8-bit wide ROMs are common there couldremain 5 bits surplus when two are used.

These 5 bits could be used and are sufficient to aid the evaluation of arunning sum and to provide the important information whether the numberof transitions in a word is odd or even and the sign and magnitude ofthe change. None of these bits is essential since the information may bederived from the transition information but this information may make iteasier to achieve fast operation and simplify running sum computation.

It may be useful to note that the code with six transitions at timeslots 0,3,6,9,12 and 15 is not used; this might be useful forsynchronisation. The continuation 2, 5, 8, 11 and 14 is used for level 5Code Book `A`. Another useful feature for synchronisation is that atransition in time slot 14 never preceeds any word in Code Book `B`.

The constraints used in the Code Books are that no transitions are lessthan 3 or more than 12 time slots apart with the exception that betweentransitions in adjacent words the maximum separation may occasionally be15 time slots; the latest first transition is in time slot 9 and theearliest last transition is in time slot 10 ignoring the cases where afurther transition is forced to occur in time slots 0 or 1 in thefollowing word.

FIG. 6 shows the above described arrangement in more detail. An 8-bitinput latch feeds the information word to be carried as an address for a10×16 programmed ROM 62. Outputs D_(o) -D₁₀ of the ROM 62 are fed to sixassemblies of latches 63-68 and are operated thereby in accordance withthe truth tables shown in FIG. 7.

The assemblies of latches 68-68 transform the eleven outputs D_(o) -D₁₀from ROM 62 into sixteen signals, fifteen of which are fed through afurther block of latches 70 clocked a word frequency and into a parallelto series converter 71. The output of the converter 71 os fed through adivide-by-two circuit 72 and an output latch 73 which is clocked at bitrate e.g. sixteen times word rate.

The sixteenth signal from the assemblies of latches is used to indicatewhether Code Book `A` or `B` should be used; if the sixteenth signal isa `O` Code Book `A` is used for the next word while if the signal is a`1` Code Book `B` is used. The sixteenth signal is fed through a latch75 clocked at word frequency and the output of the latch 75 is fed as aninput to latch assembly 63 and as an address bit to the ROM 62.

Outputs D₁₁ -D₁₄ of the ROM 62 are assembled in an accumulator 76 andthe sixteenth output D₁₅ is added to or subtracted from the signal inthe accumulator 76 after being fed through a latch 77 and adivide-by-two-circuit 78. The output of the accumulator is used as thetenth addressing input to the ROM 62.

As shown in FIG. 8, the accumulator 76 may be constructed from a modulo256 counter circuit 76a which feeds an 8-bit latch 76b. PROM 62 contains1024 words of 16 bits and is addressed chiefly by the 8 bit words (A₀ toA₇) containing the information to be carried. However, there are twofurther address bits A₈ and A₉. It is convenient to consider that if A₈is `zero` then Code Book `A` will be used whereas Code Book `B` will beused if A₈ is in the `one` state. For each of these code books some ofthe words output from the PROM will differ depending on the state A₉ ;the state of A₉ is controlled by the most significant bit of anaccumulator which will be assumed to operate in module 256 Initiallythis should be set to represent a 128 state (127 would also be usable)but 128 will be assumed. If the state is in the range 128 to 255inclusive then A₉ will be high and this selects `opposite`, if the stateis in the range 0 to 127 inclusive `same` will be selected.

All the inputs to the parallel to serial converter 71 are in the `zero`state except for those where transitions are required; these are in a`one` state. Whenever a `one` state reaches the output of the parallelto serial converter 71 the divide-by-two circuit 72 changes state socausing the production of a transition.

Knowing the required transition patterns, the patterns of data D₀ to D₁₀may be derived from consideration of the Truth Tables shown in FIG. 7.Note however that for `A` words the state of D₀ is irrelevant and thatD₉ and D₁₀ are both `ones` when the following word is required to befrom the `B` Code Book.

For the embodiment shown there remain 5 bits D₁₁ -D₁₅, of the 16 outputbits, that are not used for the information being carried. These may beused for evaluating the running-sum rapidly. The running sum is usuallydefined for NRZ as follows. At the initial start of data the running-sumis assumed to be zero. As each succeeding bit occurs the running-sum isincremented by one if the bit represents a `one` whilst it isdecremented by one if the bit represents a `zero`. For NRZ after an evennumber of bits the running-sum must be even. With this method ofrunning-sum calculation the running-sum at the end of the word onlybecomes available after the start of the last bit of the word.

With the 2/3 coder a choice needs to be made for the next word to becoded dependent on the running-sum which will exist at the end of thecurrent word. The variation of the running-sum during a word can neverbe greater than the range ±8; the extreme values would only occur if notransitions occurred within a word. It is assumed when the running-sumis computed that a state is counted as ±1/2 per half bit-cell. For aneven number of half bit-cells the possible sum variations during a wordalways have integer values.

For code-books which are practical there will always be at least onetransition in a word preventing the extremes of the range being used soa four bit number, capable of representing the number range -8 to +7,will always be sufficient. It is convenient to represent zero variationby the binary number 0000 and to add decimal 16 to negative numbers. Themodulo 16 numbers can be changed to the appropriate modulo 256 numbersby applying the D₁₁ input to the adder also to the higher significanceinputs as shown in FIG. 8.

It is suggested that the running-sum variation during a word should bethe one starting from the centre of half-cell `O` up to the same pointon the following word and that it be assumed that the state prior to thestart should be `one`.

Since the polarity of the signal immediately before the start ofhalf-cell `O` will reverse each time a previous word has an odd numberof transitions it is necessary to appropriately switch the accumulatorfrom addition to subtraction. This is achieved by making D₁₅ a `one` inall cases where the number of transitions in a word is odd. At the endof that word the divide by two changes state so switching theaccumulator from add to substract or vice versa at the appropriatetimes.

There are many requirements of the replay circuitry which areunconnected with the channel code used and these will not be consideredand it will be assumed that, a transition causes a `1` state lasting onetime slot, that clocks at twice the bit cell frequency and that wordframing are available.

The important step is how to reduce a pattern of transitions which maybe occurring at 16 different points per word into say 10 or 11 binarydigits used for addressing a ROM of practical size.

There are two approaches of interest. One is based on auxilliary ROMs.Only 28 different combinations of valid transition patterns may occur ineight adjacent time slots; this number can be portrayed by 5 bits. Asmall read only memory with 256 address locations would be used for thispurpose and the speed could be so high that the same ROM could be usedtwice per word rather than to use two identical ROMs. This method canincorporate the checking of the minimum separation of transitions ofthree time slots. Table 2 shows the relationship between the number of,adjacent time slots, possible patterns and the number of bits; inpractice some limitations such as the first transition occurring nolater than time slot 8 (ninth time slot) may be used to slightlydecrease the number of possible patterns if this is high. It isdesirable that at least one additional pattern be available so thatfaulty operation can be signalled when two transitions are apparentlyseparated by less than three time slots.

                  TABLE 2                                                         ______________________________________                                        No. of time slots                                                                        3     4     5   6   7   8   9   10  11  12                         No. of patterns                                                                          4     6     9   13  19  28  41  60  88  129                        No. of bits                                                                              2     3     4   4   5   5   6   6   7   7?                         ______________________________________                                    

The alternative method which uses no auxilliary ROM is shown in FIG. 9.

Before describing FIG. 9 in detail it is necessary to recall that thereis a time slot clock running at double the frequency of the word frameclock and also that in the code words there must be at least three timeslots between adjacent transitions. This latter feature requires that afurther clock signal be generated where frequency is 1/3 the time slotclock frequency.

Turning now to FIG. 9, incoming serialized code words are fed through aseris of latches 101, 102, 103 clocked at time slot frequency whichtogether with EXCLUSIVE OR gates 106 and 107 form a data validationsection. The output from gate 106 is fed through a series of latches111-115 clock at 1/3 the time slot frequency while the output from thegate 107 is fed through another series of latches 121-125 also clockedat 1/3 the time slot frequency. The outputs from the latches 111-115 and121-125 constitute ten inputs to an 11-input latch 130 which is clockedat word frame frequency. The eleventh input to the latch 130 is derivedfrom a further latch 104 which is with the incoming serialized codewords. Every three time slots the latches 111 and 121 capture theinformation derived from outputs A, B and C of the latches 101, 102, 103and have the states 01, 10 and 11 for transitions at A, B and Crespectively. If A, B and C all have no transition present these latcheshave the state 00. After a word, the information derived from 15 of the16 time slots, time slots 0-14, appears at the output of latches 111-115and 121-125 in coded form. The information for time slot 15 is capturedby the latch 104. It will also have previously captured the presence oftransitions at time slots 3, 6, 9 and 12 but these are ignored. Theeleven input latch 130 operates once per word and transfers the datathen present at its inputs to the address inputs of a ROM 131 whichcontains the data necessary to convert the coded data into the originaldigital words, i.e. the information relating to both code books `A` and`B`. At the same time the 8 data outputs from the ROM for the previousword are captured by the output latch 132. For this system it isnecessary to check for invalid data where transitions occur at less thanthree time slots separation. If, during a word, A and C or B and C aresimultaneously both `ls` the word is invalid. This may either be used asa `flag` on the word but a possible alternative or addition would be toclear the input latch to the ROM when the word is entering and toreserve one output state, for example all `ones`, which may need to beexcluded from the normal signal range.

I claim:
 1. A method of processing digital information prior torecording, comprising the steps of:inputting a succession of digitalwords each comprising a plurality of bit locations; generating arespective code word for each digital word, with each word having thesame period as the input digital word but a number of time slots whichis twice the number of bit locations in an input digital word, each codeword having a minimum spacing of a period equal to the period of threetime slots between adjacent transitions; providing a running sum whosevalue depends on the number and spacing of transitions in successivelygenerated code words; and providing four groups of code words from whicheach successive code word is generated, the four groups comprising firstand second group pairs, the code word generated for a particular digitalword being generated from the particular group in a group pair as afunction of the polarity of the running sum; defining a predeterminedadjacent pair of time slots, being the same time slots for each codeword, code words in the first group pair having no transitions in thepredetermined time slots, and code words in the second group pair havinga transition in one or other of the predetermined time slots; the codeword generated for a particular digital word being generated from thefirst or second group pair in dependence on the immediately precedingcode word, and if the code word is to be generated from the second grouppair, the position of the transition within the predetermined pair oftime slots is dependent on the particular digital word that is beingcoded.
 2. A method in accordance with claim 1, wherein for some, but notall of the digital words, respective code words in each group of a grouppair are identical.
 3. A method in accordance with claim 1, wherein thecode words included in each group of a group pair are initiallyallocated to the particular group from a consideration of the runningsum variation which their selection for processing would cause.
 4. Amethod in accordance with claim 1, wherein the running sum is updatedfor each successive code word at the same time as the code word is beingselected, by monitoring the characteristics of the code word as it isbeing selected.
 5. Apparatus for processing digital information prior torecording, comprising:a memory device containing information relating tofour groups of code words, the groups comprising first and second grouppairs; means for addressing the memory device with an input digital wordto output information relating to a desired code word for the inputdigital word from one of the four groups, each code word having the sameperiod as the period of the input digital word but a number of timeslots which is twice the number of bits than in the digital word, eachcode word having a minimum spacing of a period equal to the period ofthree time slots between adjacent transitions; means for monitoring thecode word and for addressing the memory device for a succeeding codeword, and comprising means for computing a running sum whose valuedepends on the number and spacing of transitions in successivelygenerated code words, such that the succeeding code word is chosen onthe basis of the preceding code word, the state of the running sum, andthe input digital word; a predetermined adjacent pair of time slotsbeing defined for each code word, being the same time slots for eachcode word, code words in the first group pair having no transitions inthe predetermined time slots, and code words in the second group pairhaving a transition in one or the other of the predetermined time slots;and the means for addressing the memory device for a succeeding codeword being arranged such that the code word generated for a particulardigital word is generated from the first or second group pair independence on the immediately preceding code word, and if the code wordis to be generated from the second group pair, the position of thetransition within the predetermined pair of time slots is dependent onthe particular digital word that is being coded.
 6. Apparatus accordingto claim 5, wherein the information generated by the memory means isinput to a code converter to generate a code word.
 7. Apparatusaccording to claim 6, wherein a series of groups of latches areconnected to outputs of the meory device to generate the code words. 8.Apparatus according to claim 5, wherein the means for monitoring causesproduction of digital information indicative of whether there are an oddor even number of transitions in the code word being generated andindicative of the change in magnitude of the running sum, and thedigital information is produced by the monitoring means at the same timeas the code word is being generated.